The present invention relates to a data output circuit of a semiconductor memory integrated circuit device.
Semiconductor memory integrated circuit devices having a mechanism for outputting read signals from a memory array to data output terminals as shown in FIG. 2 have been known.
The operation thereof will be described with reference to the drawings. To make the description more concrete and clearer, it will be focused on a semiconductor nonvolatile memory device comprised of electrically rewritable nonvolatile memory cells.
In order to improve data processing efficiency per unit operation, most general memory devices use a plurality of data structures, and the following description will be focused on devices having a data length of eight bits (one byte).
Nonvolatile memory cells are arranged in the form of a matrix in a memory array 1. To read one byte of memory contents, a signal is first input to word selection signal input lines 2 to select and validate one of a plurality of word lines.
Read output signals from nonvolatile memory cells for a plurality of bytes selected as described above are transmitted to a column selector 4, and only read output signals of one byte are transmitted to read signal buses 5 in accordance with a signal input to column selection signal input lines 3.
Then, the one byte of signals for the selected nonvolatile memories which have been transmitted to the read signal buses 5 are subjected to signal amplification by eight sense amplifiers 6 and are output to data input/output terminals 8 through output buffers 7.
The above-described series of operation is referred to as a "read operation" and is performed not only in nonvolatile memories but also in SRAM's and DRAM's.
The signals readout from the memory cells selected from among the memory array 1 are amplified and determined by the sense amplifier 6 and are assigned to a logical amplitude of "0" or "1". In the case of a nonvolatile memory cell, however, the amplitude of a signal readout from a memory cell is inherently continuous and is not expressed as a binary potential in a logical amplitude. In this case, therefore, what is important is the magnitude of the threshold voltage of a nonvolatile memory cell transistor 19 (see FIG. 4). Then, for the purpose of checking the state of memory cells in greater detail, a means is provided for outputting signal on the read signal buses 5, to which the signal out from the memory cells is transmitted, to the data input/output terminals 8 through a read signal transmission transistor 9. This makes it possible to check the state of the memory cells which have been selected from the memory array 1 in detail.
In a normal read operation using sense amplifiers, it is not possible to check the state of memory cells which can continuously change as a continuous quantity. Therefore, as described above, the read signal transmission transistor 9 is provided to apply a signal to a test signal input TA 10, thereby allowing the measurement of the state of the memory cells, more specifically, the threshold voltage thereof. This is a widely followed practice for semiconductor integrated memory circuits utilizing nonvolatile memory cells. It is very important in testing semiconductor memory integrated circuits to eliminate (screen) IC chips having initial defects and reliability problems.
The measurement of the threshold voltage will be further described. FIG. 4 shows an example of the configuration of a nonvolatile memory array illustrating the contents of the memory array 1 shown in FIG. 2 in greater detail.
A nonvolatile memory cell 21 as one memory unit is constituted by a transistor for selection 18 and a nonvolatile memory cell transistor 19. The transistor for selection 18 is an enhancement-type transistor which has a positive threshold voltage and is turned on and off by signals applied to a word line 16. On the other hand, the threshold voltage of the nonvolatile memory cell transistor 19 continuously changes from a depletion type to an enhancement type due to its unique structure. In addition, the threshold voltage is characterized in that it is maintained even when the power supply of the IC is disconnected.
The word selection signal input lines 2 are connected to the word lines 16. One word line is selected from among the plurality of word lines arranged to horizontally extend in FIG. 4. As a result, the drain side of the nonvolatile memory cell transistor 19 is connected to a bit line 17 through the transistor for selection 18. On the other hand, the bit lines 17 arranged to vertically extend are connected to the column selector 4 in FIG. 2, and are output to data input/output terminals 8 through a read bus 5 and the read signal transmission transistor 9.
In this state, the state of the nonvolatile memory cell transistor 19 can be determined by connecting a voltage source to the data input/output terminal 8 and by measuring the current flowing into the IC chip. Further, it is apparent that the state of the nonvolatile memory cell transistor 19 can be measured in greater detail if it is possible to apply a variable voltage to a control gate electrode 20 of the nonvolatile memory cell transistor 19 from the outside of the IC chip.
In conventional configurations of memory read circuits, however, in order to make detailed measurement of the state of memory cells, a plurality of data input/output terminals must be measured one by one by connecting them to a voltage source and a current measuring device. This has resulted in a problem especially in the case of semiconductor memory integrated circuits having a large data length in that measurement of the entire memory array takes an extremely long time.
In addition, in the field of semiconductor memory integrated circuits, there is a problem in that increasing memory capacity of such devices has been expanding the time required for testing the IC chips during the inspection of the same. It is desired to increase the number of IC chips tested in a limited period of time without reducing the quality of the testing. What is needed is to improve throughput with the quality of inspections on IC chips maintained.
Under the circumstances as described above, a plurality of IC chips are simultaneously measured in actual inspection steps for semiconductor memory integrated circuits. However, limitations on inspection equipments place a limit on the quantity of IC chips which can be simultaneously measured. Since the numbers of drivers, comparators, and DC measuring units included in an inspection equipment is limited, the number of IC chips which can be simultaneously measured is reduced with an increase in the number of terminals of an IC chip.